Active-HDL Microsoft Windows XP/Vista Only DOWNLOAD NOW! FPGA Design and Simulation
	ALINT Microsoft Windows XP/Vista, Linux 32/64bit DOWNLOAD NOW! ASIC/FPGA Design Rule Checking
	Riviera-PRO Microsoft Windows XP/Vista, Linux 32/64bit DOWNLOAD NOW!  ASIC/FPGA Design and Simulation

 

Aldec HDL Simulators, Active-HDL™ and Riviera-PRO™, offer a complete verification environment including design creation, common kernel HDL simulation with advanced debugging and coverage tools. Our mixed-language simulators support VHDL, Verilog®, SystemVerilog, SystemC and Assertions (SVA, PSL & OVA) for FPGA and ASIC designs. ALINT™ is an RTL design analysis tool that identifies design issues/errors early in the development cycle, saving you from costly mistakes.

Supported Languages:

• VHDL IEEE 1076 (1987, 1993, 2002 and 2008)
• Verilog® HDL IEEE 1364 (1995, 2001 and 2005)
• SystemC™ 2.2 IEEE 1666/OSCI 2.2
• SystemVerilog IEEE 1800 (Design)
• SystemVerilog IEEE 1800 (Verification)
• SystemVerilog IEEE 1800 DPI 2.0
• SystemVerilog IEEE 1800 (Assertions)
• PSL IEEE 1850
• EDIF 2 0 0
• Single or Mixed Language